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LE25S40MB
13. Hardware Data Protection
LE25S40MB incorporates a power-on reset function. The following conditions must be met in order to ensure that the
power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 18 Power-down Timing
VDD
VDD(Max)
VDD(Min)
tPD
0V
Power-on timing
vBOT
Parameter
Symbol
min
spec
max
unit
power-on to operation time
power-down time
power-down voltage
tPU
tPD
tBOT
100
10
0.2
μs
ms
V
14. Software Data Protection
The LE25S40MB eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
? When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
? When the page program data is not in 1-byte increments
? When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1 μ F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure
that the device will operate stably.
No.A2096-15/22
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